1. Field of the Invention
The present invention relates to an array substrate, and more particularly, to an array substrate including a thin film transistor with an oxide semiconductor layer and a method of fabricating the same.
2. Discussion of the Related Art
With rapid development of information technologies, display devices for displaying a large amount of information have been promptly developed. More particularly, flat panel display (FPD) devices having a thin profile, light weight and low power consumption such as organic electroluminescent display (OLED) devices and liquid crystal display (LCD) devices have been actively pursued and are replacing the cathode ray tubes (CRTs).
Among the liquid crystal display devices, active matrix type liquid crystal display devices, which include thin film transistors to control on/off the respective pixels, have been widely used because of their high resolution, color rendering capability and superiority in displaying moving images.
In addition, organic electroluminescent display devices have been recently spotlighted because they have many merits as follows: the organic electroluminescent display devices have high brightness and low driving voltages; because they are self-luminous, the organic electroluminescent display devices have excellent contrast ratios and ultra thin thicknesses; the organic electroluminescent display devices have a response time of several micro seconds, and there are advantages in displaying moving images; the organic electroluminescent display devices have wide viewing angles and are stable under low temperatures; since the organic electroluminescent display devices are driven by a low voltage of direct current (DC) 5V to 15V, it is easy to design and manufacture driving circuits; and the manufacturing processes of the organic electroluminescent display device are simple since only deposition and encapsulation steps are required. In the organic electroluminescent display devices, active matrix type display devices also have been widely used because of their low power consumption, high definition and large-sized possibility.
Each of the active matrix type liquid crystal display devices and the active matrix type organic electroluminescent display devices includes an array substrate having thin film transistors as switching elements to control on/off their respective pixels.
FIG. 1 is a cross-sectional view of illustrating an array substrate for a liquid crystal display device or for an organic electroluminescent display device according to the related art. FIG. 1 shows a cross-sectional view of a pixel region including a thin film transistor in the array substrate.
In FIG. 1, gate lines (not shown) and data lines 33 are formed on a substrate 11 and cross each other to define pixel regions P. A gate electrode 15 is formed at a switching region TrA of each pixel region P. A gate insulating layer 18 is formed on the gate electrode 15, and a semiconductor layer 28, which includes an active layer 22 of intrinsic amorphous silicon and ohmic contact layers 26 of impurity-doped amorphous silicon, is formed on the gate insulating layer 18. Source and drain electrodes 36 and 38 are formed on the ohmic contact layers 26. The source and drain electrodes 36 and 38 correspond to the gate electrode 15 and are spaced apart from each other. The gate electrode 15, the gate insulating layer 18, the semiconductor layer 28, and the source and drain electrodes 36 and 38 sequentially formed at the switching region TrA constitute a thin film transistor Tr.
A passivation layer 42 is formed on the source and drain electrodes 36 and 38 and the exposed active layer 22. The passivation layer 42 has a drain contact hole 45 exposing a portion of the drain electrode 38. A pixel electrode 50 is formed independently in each pixel region P on the passivation layer 42. The pixel electrode 50 contacts the drain electrode 38 through the drain contact hole 45. Here, a semiconductor pattern 29 is formed under the data line 33. The semiconductor pattern 29 has a double-layered structure including a first pattern 27 of the same material as the ohmic contact layers 26 and a second pattern 23 of the same material as the active layer 22.
In the semiconductor layer 28 formed at the switching region TrA of the related art array substrate, the active layer 22 of intrinsic amorphous silicon has different thicknesses depending on the position. That is, a portion of the active layer 22 exposed by selectively removing the ohmic contact layers 26 has a first thickness t1 and a portion of the active layer 22 under the ohmic contact layers 26 has a second thickness t2, which is thicker than the first thickness t1. The different thicknesses of the different portions of the active layer 22 are caused by a manufacturing method, and this decreases the output characteristics of the thin film transistor Tr and negatively affects the performance of the thin film transistor Tr because the active layer 22 between the source and drain electrodes 36 and 38, which becomes a channel of the thin film transistor Tr, has a reduced thickness.
To address this problem, a thin film transistor having an oxide semiconductor layer of a single layer, which does not need the related art ohmic contact layers and which uses an oxide semiconductor material as an active layer, has been developed.
FIG. 2 is a cross-sectional view of an array substrate including a thin film transistor having such an oxide semiconductor layer according to the related art. In FIG. 2, the thin film transistor Tr is formed on a substrate 51 and includes a gate electrode 53, source and drain electrodes 57 and 59, and an oxide semiconductor layer 61. A gate insulating layer 55 is disposed between the gate electrode 53 and the source and drain electrodes 57 and 59. A passivation layer 63 covers the thin film transistor Tr and has a contact hole 65 exposing the drain electrode 59. A pixel electrode 67 is formed on the passivation layer 63 and is connected to the drain electrode 59 through the contact hole 65.
In the thin film transistor Tr of FIG. 2 having the oxide semiconductor layer 61, ohmic contact layers are not required and are not provided, and thus the oxide semiconductor layer 61 is not exposed to etching gases used in a dry-etching process. Therefore, lowering of the output characteristics of the thin film transistor Tr is prevented or minimized.
On the other hand, since the oxide semiconductor layer 61 does not have an etch selectivity to a metal layer, the oxide semiconductor layer 61 may be removed or damaged by an etchant for etching the metal layer when the oxide semiconductor layer 61 is exposed to the etchant. The characteristics and performance of the thin film transistor may be negatively affected.
Accordingly, in FIG. 2, the thin film transistor Tr has a structure in which the source and drain electrodes 57 and 59 are formed, and then the oxide semiconductor layer 61 is formed on the source and drain electrodes 57 and 59.
However, in the thin film transistor Tr having the oxide semiconductor layer 61 on the source and drain electrodes 57 and 59, which are formed of a metallic material, there may be a problem such as poor adhesion.
In addition, as shown in the enlarged region A in FIG. 2, the oxide semiconductor layer 61 may be disconnected or may be very thin around the sides of the source and drain electrodes 57 and 59 facing each other due to the step profile at a region including a portion of the gate insulating layer 55 exposed between the source and drain electrodes 57 and 59, and at portions of the source and drain electrodes 57 and 59. Therefore, the thickness of the oxide semiconductor layer 61 is not uniform, and the performance characteristics of the thin film transistor Tr are lowered.
In view of these limitations of the thin film transistors of FIGS. 2 and 3, an etch stopper has been introduced to prevent an oxide semiconductor layer from being exposed to an etchant. FIG. 3 is a cross-sectional view of an array substrate including a thin film transistor having an oxide semiconductor layer and an etch stopper according to the related art.
In FIG. 3, the thin film transistor Tr is formed on a substrate 71 and includes a gate electrode 73, source and drain electrodes 81 and 83, and an oxide semiconductor layer 77. The thin film transistor Tr further includes an etch stopper 79 on the oxide semiconductor layer 77 between the source and drain electrodes 81 and 83 such that a central portion of the oxide semiconductor layer 77 is not exposed to an etchant when the source and drain electrodes 81 and 83 are formed. The etch stopper 79 may be formed of an inorganic insulating material.
A gate insulating layer 75 is disposed between the gate electrode 73 and the oxide semiconductor layer 77. A passivation layer 85 covers the thin film transistor Tr and has a contact hole 87 exposing a portion of the drain electrode 83. A pixel electrode 89 is formed on the passivation layer 85 and is connected to the drain electrode 83 through the contact hole 87.
However, the array substrate of FIG. 3 including the thin film transistor Tr that has the oxide semiconductor layer 77 and the etch stopper 79 thereon is manufactured through a mask method composed of six (6) mask processes where one mask process is added to form the etch stopper 79. That is, there are six mask processes involved in the related art mask method for forming the array substrate, where a first mask process is used for forming the gate electrode, a second mask process is used for forming the oxide semiconductor layer, a third mask process is used for forming the etch stopper, a fourth mask process is used for forming the source and drain electrodes, a fifth mask process is used for forming the contact hole in the drain electrode, and a sixth mask process is used for forming the pixel electrode.
However, each of these six mask processes includes the steps of applying a photoresist material on a layer desired to pattern, exposing the photoresist material to light though a single photo mask, developing the light-exposed photoresist material and thereby forming a photoresist pattern, etching the layer using the photoresist pattern, and stripping the photoresist pattern. Thus, each mask process is complicated and many chemical solutions are used. As such, as the number of mask processes in the mask method increases, the manufacturing time lengthens. Therefore, in the related art method and device, the productivity is lowered, more defects are generated, and the manufacturing costs are raised.
Accordingly, in the array substrate of FIG. 3 according to the related art, there is a need to lower the manufacturing cost of the array substrate as well as to simplify the mask method by reducing the number of mask processes in the mask method for forming the thin film transistors.